报告题目：Active Learning and Graph Learning in EDA

报告人：余备, 香港中文大学助理教授

报告时间：2019年8月8日(周四) 上午10：00 — 12:00

报告地点：数计学院4号楼229室

报告摘要：

Machine learning is a powerful technique that can derive knowledge from large data set, and provide prediction and modeling. Since VLSI chip designs have extremely high complexity and gigantic data, recently there has been a surge in applying and adapting machine learning to accelerate the design closure. In this talk, we focus on some key techniques and recent developments of machine learning on chip designs. Two case studies will be provided: active learning based Pareto curve learning and graph learning based testing point insertion.

报告人简介：

Prof. Bei Yu received his Ph.D. degree from the Department of Electrical and Computer Engineering, University of Texas at Austin in 2014. He is currently an Assistant Professor in the Department of Computer Science and Engineering, The Chinese University of Hong Kong. He has served as TPC Chair of ACM/IEEE Workshop on Machine Learning for CAD (MLCAD) 2019, served in the program committees of DAC, ICCAD, DATE, ASPDAC, ISPD, the editorial boards of Integration, the VLSI Journal, and IET Cyber-Physical Systems: Theory & Applications. He is Editor-of-Chief of IEEE TCCPS Newsletter. He has received five Best Paper Awards from Integration, the VLSI Journal in 2018, ISPD 2017, SPIE Advanced Lithography Conference 2016, ICCAD 2013, and ASPDAC 2012, three other Best Paper Award Nominations at DAC 2014, ASPDAC 2013, ICCAD 2011, and four ICCAD/ISPD contest awards.